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| A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver Features and Benefits Serial interface for full digital control Dual full-bridge gate drive for N-channel MOSFETs Dual 6-bit DAC current reference Operation over 12 to 50 V supply voltage range Synchronous rectification Cross-conduction protection Adjustable mixed decay Fixed off-time PWM current control Low-current idle mode Description The A3985 is a flexible dual full-bridge gate driver suitable for driving a wide range of higher power industrial bipolar 2phase stepper motors or 2-phase brushless dc motors. It can also be used to drive two individual torque motors or solenoid actuators. Motor power is provided by external N-channel power MOSFETs at supply voltages from 12 to 50 V. Full digital control is provided by two serially-accessible registers that allow programming of off-time, blank-time, dead-time, mixed decay ratios, synchronous rectification, master clock source selection, and division ratio and idle mode. All internal timings are derived from a master clock that can be generated on-chip or provided by an external clock such as the system clock of the master controller. A programmable divider allows for a wide range of external system clock frequencies. The internal fixed off-time PWM current-control timing is programmed via the serial interface to operate in slow, fast, and mixed current-decay modes. The desired load-current level and direction is set via the serial port with a direction bit and two 6-bit linear DACs in conjunction with a reference voltage. The seven bits of control allow maximum flexibility in torque Continued on the next page... Package: 38 pin TSSOP (suffix LD) Approximate size Typical Application 3985-DS A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver are protected from shoot-through by integrated crossover-control and programmable dead time. In addition to crossover current control, internal circuit protection provides thermal shutdown with hysteresis and undervoltage lockout. Special power-up sequencing is not required. This component is supplied in a 38-pin TSSOP (package LD) with 100% matte tin leadframe plating. Description (continued) control for a variety of step methods, from microstepping to full-step drive. Load current in the external power MOSFET full-bridges is set in 1.56% increments of the maximum value. The above-supply voltage required for the high-side N-channel MOSFETs is provided by a bootstrap capacitor. Efficiency is enhanced by using synchronous rectification and the power FETs Selection Guide Part Number A3985SLD-T A3985SLDTR-T Packing* Tube, 50 pieces per tube Tape and reel, 4000 pieces per reel *Contact Allegro for additional packing options Absolute Maximum Ratings Characteristic Supply Voltage Logic Supply Voltage Logic Inputs and Outputs SENSEx pins Sxx pins LSSx pins GHxx pins GLxx pins Cxx pins Operating Ambient Temperature Junction Temperature Storage Temperature TA TJ(max) Tstg Range S Symbol VBB VDD Notes Rating -0.3 to 50 -0.3 to 7 -0.3 to 7 -1 to 1 -2 to 55 -2 to 5 Sxx to Sxx+15 -2 to 16 V -0.3 to Sxx+15 -20 to 85 150 -55 to 150 Units V V V V V V V V V C C C Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver Functional Block Diagram +5 V VDD VBB VMOTOR VREG Bandgap Regulator CREG Phase 1A Bridge1 CBOOT1A REF VREF High-Side Drive VREG 6-bit DAC Low-Side Drive GL1A LSS1 SENSE1 Phase 1B Low-Side Drive Phase 1 SDI Phase 1 Control Logic High-Side Drive GH1B CBOOT1B C1B STR Serial Port GL1B S1B RSENSE1 P P C1A GH1A S1A RGH1A RGH1B RGL1A RGL1B SDO Programmable PWM Timer Blanking Mixed Decay VMOTOR Bridge2 Phase 2A C2A CBOOT2A SCK Phase 2 Control Logic Phase 2 High-Side Drive VREG Low-Side Drive GH2A S2A RGH2A RGH2B GL2A LSS2 SENSE2 RGL2A RGL2B WC Programmable PWM Timer Blanking Mixed Decay Phase 2B Low-Side Drive GL2B S2B GH2B CBOOT2B C2B RSENSE2 P 6-bit DAC ENABLE VREF Programmable Divider Oscillator Protection UVLO TSD High-Side Drive OSC GND Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS at TA = 25C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise Characteristics Supply and Reference Load Supply Voltage Range Load Supply Current Load Supply Idle Current Logic Supply Voltage Range Logic Supply Current Logic Supply Idle Current Regulator Output Bootstrap Diode Forward Voltage Gate Output Drive Turn-On Rise Time Turn-Off Fall Time Turn-On Propagation Delay Turn-Off Propagation Delay Crossover Dead Time Pull-Up On Resistance Pull-Down On Resistance Short-Circuit Current - Source1 Short-Circuit Current - Sink GHx Output Voltage GLx Output Voltage Logic Inputs Input Low Voltage Input High Voltage Input Hysteresis Input Current1 Output Low Voltage Output High Voltage Output Leakage current1 Symbol VBB IBB IBBQ VDD IDD IDDQ VREG VfBOOT tr tf tp(on) tp(off) tDEAD fMCK = 4 MHz, CLOAD = 1000 pF ENABLE = High, outputs disabled Word1:Bit D18 = 0 Test Conditions Min. 12 - - - 3.0 - - 11.25 0.6 80 40 - - 0.5 30 14 -140 160 VC - 0.2 VREG - 0.2 - 0.7 VDD 150 -1 SDO, IOL= 0.5 mA SDO, IOH= -0.3 mA SDO, STR = 1, 0 V< VO< VDD VDD - 0.5 -1 1 Typ. - - - - - - - - 0.8 120 60 120 120 - 40 19 -110 200 - - - - 300 - Max. 50 10 6 100 5.5 10 300 13 1 160 80 - - 0.75 55 24 -80 250 - - 0.3 VDD - - 1 0.5 Units V mA mA A V mA A V V ns ns ns ns s mA mA V V V V mV A V V A Word1:Bit D18 = 0 IREGInt = 30 mA IfBOOT = 10 mA CLOAD = 1000 pF, 20% to 80% CLOAD = 1000 pF, 80% to 20% ENABLE low to gate drive on ENABLE high to gate drive off fMCK = 4 MHz, Word1:Bits D1 and D2 = 00 IGH = -25 mA IGL = 25 mA RDS(on)UP RDS(on)DN ISC(source) ISC(sink) VGHx CBOOTx fully charged VGLx VIL VIH VIHys IIN VOL VOH IOleak Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS, continued, at TA = 25C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Current Control fMCK = 4 MHz; Blank Time tBLANK - 1 - Word1:Bits D1 and D2 = 00 fMCK = 4 MHz, Word1:Bits D3 to D7 = 01010, and 21.75 - 22 Fixed Off-Time tOFF D15 = 0 Reference Input Voltage VREF 0.8 - 2 Internal Reference Voltage VREFInt 20 k to VDD 1.9 2.0 2.1 Current Trip Point Error2 EITrip VREF = 2 V - - 5 1 Reference Input Current IREF -3 0 3 Internal Oscillator Frequency fOSC ROSC = 10 k 3.2 4 4.8 Maximum Clock Input Frequency fEXTmax External clock selected - 10 - Master Clock Frequency fMCK 0.5 4 5 Protection VREG Undervoltage Lockout VREGUV Decreasing VREG 7.5 8 8.5 VREG Undervoltage Lockout VREGUVHys 100 200 - Hysteresis Decreasing VDD 2.45 2.7 2.95 VDD Undervoltage Lockout VDDUV VDD Undervoltage Lockout VDDUVHys 50 100 - Hysteresis Overtemperature Shut Down TTSD Temperature increasing - 165 - Overtemperature Shut Down - 15 - TTSDHys Recovery = TTSD - TTSDHys Hysteresis Units s s V V % A MHz MHz MHz V mV V mV C C Continued on the next page... THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Symbol RJA Test Conditions* 4-layer PCB, based on JEDEC standard 1-layer PCB with copper limited to solder pads Value Units 47 114 C/W C/W *Additional thermal information available on Allegro Web site. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS, continued, at TA = 25C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Serial Data Timing Serial Clock High Time Serial Clock Low Time tSCKH tSCKL 50 50 Units ns ns ns Strobe Lead Time tSTLD 30 ns Strobe Lag Time tSTLG 30 ns Strobe High Time tSTRH 150 ns Data Out Enable Time tSDOE 40 - ns Data Out Disable Time tSDOD 30 - ns Data Out Valid Time from SCK Falling tSDOV 40 - ns Data Out Hold Time from SCK Falling tSDOH 5 - ns Data In Set-up Time to SCK Rising tSDIS 15 - ns Data In Hold Time from SCK Rising tSDIH 10 - ns WC Set-up Time to STR Rising tSWCS 15 - ns WC Hold Time from STR Rising tSWCH 50 - ns WC Hold Time from STR Falling tSLWCH 30 - 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2Current Trip Point Error is the difference between actual current trip point and the target current trip point, referred to full scale (100%) current: EITrip = 100 x (ITripActual - ITripTarget) / IFullScale % - - - - - - - - - - - - - - - - - - - Serial Data Timing Diagram WC tSLWCH tSWCS tSWCH STR tSTLD tSCKH tSCKL tSTLG tSTRH SCK tSDIS tSDIH SDI tSDOE tSDOV D18 tSDOH D17 D0 tSDOD SDO ** D18* D17* D0* Dx = Current data transfer block Dx* = Previous data transfer block ** = Undefined, usually LSB from previous transfer Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver Functional Description Basic Operation The A3985 is a highly-configurable dual full-bridge FET driver with built-in digital current control. All features are accessed through a simple SPI (Serial Peripheral Interface) compatible serial port, allowing multiple motors to be controlled with as few as three wires. Because the full-bridge control circuits are independently controlled, the A3985 can be used to drive 2-phase bipolar stepper motors and 2-phase brushless dc (BLDC) motors. The current in each of the two external power full-bridges (which are all N-channel MOSFETs) is regulated by a fixed off-time PWM control circuit. The full-bridge current at each step is set by the value of an external current sense resistor, RSENSEX , in the ground connection to the bridge, a reference voltage, VREF, and the output of the DAC controlled by the serial data. The use of PWM with N-channel MOSFETs provides the most cost-effective solution for a high efficiency motor drive. The A3985 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external MOSFETs are above 10 V, and that there is no crossconduction (shoot through) in the external bridge. Specific functions are described more fully in the following sections. To limit the voltage drop when the charge current is provided, this pin should be decoupled with a ceramic capacitor, CREG, to ground. The value CREG should typically be 40 times the value of the bootstrap capacitor for PWM frequencies up to 14 kHz. Above 14 kHz, the minimum recommended value can be determined from the following formula: CREG > CBOOT x 3 x fPWM , where CREG and CBOOT are in nF, and fPWM is the maximum PWM frequency, in kHz. VREG is monitored, and if the voltage becomes too low, the outputs will be disabled. REF The reference voltage, VREF, at this pin sets the maximum (100%) peak current. The REF input is internally limited to 2 V when a 20 k pull-up resistor is connected between VREF and VDD. This allows the maximum reference voltage to be set without the need for an externallygenerated voltage. An external reference voltage below the maximum can also be input on this pin. The voltage at VREF is divided by the range select ratio Gm to produce the DAC reference voltage level. OSC The PWM timing is based on a master clock, typically running at 4 MHz. The master clock period is used to derive the PWM off-time, dead time, and blanking time. The master clock frequency can be set by an internal oscillator or by one of three division ratios of an external clock. These four options are selected by bits D12 and D13 of the Control register word. When the A3985 is configured to use an external clock, this is input on the OSC pin and will usually provide more precision than using the internal oscillator. The three internal divider alternatives provide flexibility in setting the master clock frequency based on available external system clocks. If internal timing is selected, fOSC is configured by using an external resistor, ROSC, connected from the OSC pin to GND. This sets the frequency (in MHz) to approximately: fOSC 100 / (6 + 1.9 x ROSC) , where ROSC, in k, is typically between 50 k and 10 k. Power Supplies Two power connections are required. The motor power supply should be connected to VBB to provide the gate drive levels. Power for internal logic is provided by the VDD input. Internal logic is designed to operate from 3 to 5.5 V, allowing the use of 3.3 or 5 V external logic interface circuits. GND The ground pin is a reference voltage for internal logic and analog circuits. There is no large current flow through this pin. To avoid any noise from switching circuits, this should have an independent trace to the supply ground star point. VREG The voltage at this pin is generated by a low-drop-out linear regulator from the VBB supply. It is used to operate the low-side gate drive outputs, GLxx, and to provide the charging current for the bootstrap capacitors, CBOOTx. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver SDI, SCK, STR, SDO These are the serial port interface pins. Data is clocked into SDI by a clock signal on SCK. The data is then latched by a signal on STR. If required, the serial data out pin, SDO, can be used to read back the previously-latched serial data or to form a daisy chain for multiple controllers using a single STR connection. (For bit assignment details, see the Bit Assignments table.) WC This input provides a lockout capability for writing to the Control register. When set to logic high, no changes can be made to the Control register through the serial port. When at logic low, the data on the serial port will update the Control register (if selected by D0 = 1) while STR is high. This provides a mechanism to avoid inadvertently changing the Control register settings by erroneous or corrupt serial data signals. is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for the high-side N-channel power MOSFETs. The bootstrap capacitor should be ceramic and have a value of 10 to 20 times the total MOSFET gate capacitance. GH1A, GH1B, GH2A, and GH2B High-side gate drive outputs for external N-channel MOSFETs. External series gate resistors can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt at the motor terminals. GHxx = 1 (high) means that the upper half of the driver is turned on and will source current to the gate of the high-side MOSFET in the external motor-driving bridge. GHxx = 0 (low) means that the lower half of the driver is turned on and will sink current from the external MOSFET gate circuit to the respective Sxx pin. S1A, S1B, S2A, and S2B Directly connected to the motor, these terminals sense the voltages switched across the load and define the negative supply for the floating high-side drivers. The discharge current from the high-side MOSFET gate capacitance flows through these connections which should have low impedance traces to the MOSFET bridge. GL1A, GL1B, GL2A, and GL2B Low-side gate drive outputs for external N-channel MOSFETs. External series gate resistors (as close as possible to the MOSFET gate) can be used to reduce the slew rate seen at the gate, thereby controlling the di/dt and dv/dt at the motor terminals. GLxx = 1 (high) means that the upper half of the driver is turned on and will source current to the gate of the low-side MOSFET in the external motor-driving bridge. GLxx = 0 (low) means that the lower half of the driver is turned on and will sink current from the gate of the external MOSFET to the LSSx pin. LSS1 and LSS2 Low-side return path for discharge of the gate capacitors, connected to the common sources of the low-side external FETs through low-impedance traces. Gate Drive The A3985 is designed to drive external power N-channel MOSFETs. It supplies the transient currents necessary to quickly charge and discharge the external FET gate capacitance in order to reduce dissipation in the external FET during switching. The charge and discharge rate can be controlled using an external resistor, RGx, in series with the connection to the gate of the FET. Cross-conduction is prevented by the gate drive circuits which introduce a dead time, tDEAD , between switching one FET off and the complementary FET on. tDEAD is at least 2, 3, 4, or 6 periods of the master clock, depending on the corresponding value set in the Control register (Word 1: bits D1 and D2). tDEAD can be up to 1 cycle longer than the programmed value, to allow synchronization with the master clock. ENABLE This input simply turns off all of the power MOSFETs. Set to logic high to disable outputs. When at logic low, the internal control enables the outputs as required. Inputs to the registers and the internal sequencing logic are all active independent of the ENABLE input state. C1A, C1B, C2A, and C2B High-side connections for the bootstrap capacitors, CBOOTx, and positive supply for highside gate drivers. The bootstrap capacitors are charged to approximately VREG when the associated output Sxx terminal Internal PWM Current Control Each full-bridge is independently controlled by a fixed offtime PWM current control circuit that limits the load current in the phase to a desired value, ITrip. Initially, a diagonal pair of source and sink MOSFETs are enabled and current flows Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver through the motor winding and the current sense resistor, RSENSEx. When the voltage across RSENSEx equals the DAC output voltage, the current sense comparator resets the PWM latch, which turns off the source MOSFET (slow decay mode) or the sink and source MOSFETs (fast decay mode). The maximum value of current limiting is set by the selection of RSENSE and the voltage at the REF input, with a transconductance function approximated by: ITrip(max) = VREF / (Gm x RSENSE) , where Gm is the range factor defined by in the Data register (Word0: Bits D17 and D18). The DAC output reduces the VREF output to the current sense comparator, VDAC, in precise steps: VDAC = [(1 + DAC) x VREF] / 64 , where DAC is the decimal equivalent value of the Bridge DAC bits in the Data register (Word0: Bits D1 through D6 for Bridge 1, Bits 9 through 14 for Bridge 2). (Active codes are represented by the values 1 through 63. Programming a DAC input code to 0 disables the corresponding bridge, and results in minimum load current.) The current trip level for each DAC value then becomes: ITripDAC = VDAC / (Gm x RSENSE) . blanking function The blank timer is reset when PHASE is changed. The blank time can be set to 4, 6, 8, or 12 periods of the master clock by programming the blank time bits in the Control register (Word1, Bits D1 and D2) using the serial port. Dead Time To prevent cross-conduction (shoot through) in the power full-bridge, a dead time, tDEAD , is introduced between switching one MOSFET off and switching the complementary MOSFET on. The dead time, tDEAD, is nominally half of tBLANK , but may be up to 1 cycle longer to synchronize with the master clock. Mixed Decay Operation Mixed decay is a technique that provides greater control of phase currents while the current is decreasing. When a stepper motor is driven at high speed, the back EMF from the motor will lag behind the driving current. If a passive current decay mode, such as slow decay, is used in the current control scheme, then the motor back EMF can cause the phase current to rise out of control. Mixed decay eliminates this effect by putting the full-bridge initially into fast decay, and then switching to slow decay after some time. Because fast decay is an active (driven) decay mode, this portion of the current decay cycle will ensure that the current remains in control. Using fast decay for the full current decay time (off-time, tOFF) would result in a large ripple current, but switching to slow decay once the current is in control will reduce the ripple current value. The portion of the off-time that the full-bridge has to remain in fast decay will depend on the characteristics and the speed of the motor. When the phase current is rising, the motor back EMF does not affect the current control, and slow decay may be used to minimize the phase current ripple. The A3985 must be programmed to switch between slow decay, when the current is rising, and mixed decay, when the current is falling. To simplify this programming sequence the decay mode is included in the data word (Word0) with the phase current trip level and the phase current direction. When mixed decay is used, the portion of the off-time that the full-bridge remains in fast decay, tFD , is selected by pro- PWM Timer Function All bridge control timing is based on the master clock. The PWM timer is programmed via the serial port to provide fixed off-time PWM signals to the control block. The off-time, tOFF , is selected by programming the Off-Time bits in the Control register (Word1, Bits D3 through D7) using the serial port. tOFF may be up to 1 cycle longer than the programmed value, to synchronize with the master clock. Blanking When a source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load. To prevent false overcurrent detection due to this current spike, the output from the current sense comparator is ignored (blanked) for a duration of time called the blank time. The blank timer runs, when a source power MOSFET is turned on, to provide the programmable Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver gramming the Fast Decay Time bits in the Control register (Word1, Bits D8 through D11). If tFD is set longer than tOFF , the device effectively operates in full fast decay mode. Selecting between slow decay and mixed decay is done by programming the Mode bits in the Data register (Word0, Bits D8 and D16) using the serial port. be used to connect several A3985s in a serial daisy chain. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is written as two 19-bit words: 18 bits of data plus 1 bit to select the destination register. Serial Port Write Timing Operation The serial port timing requirements are specified in the electrical characteristics table, and illustrated in the Serial Data Timing diagram. Data is received on the SDI pin and clocked through a shift register on the rising edge of the clock signal received on the SCK pin. STR is normally held high, and is only brought low to initiate a write cycle. No data is clocked through the shift register when STR is high. The 18 data bits for a register are input MSB first, followed by the register select bit, D0. After D0 is clocked into the shift register, STR goes high to latch the data into the selected register. When this occurs, the internal control circuits immediately act on the new data. The Control register can only be written if the WC pin is at logic low. If WC is high and D0 = 1 (indicating the Control register), the data will be ignored on the rising edge of STR. The state of the WC pin does not affect writing to the Data register, and the pin can be tied to GND when Control register protection is not required. Note that the number of bits clocked through the shift register is irrelevant and only the last 19 bits before STR goes high will be latched. This allows several A3985 devices to be daisy-chained and updated together with a single STR rising edge. Data Register (Word 0) Bit Assignments This section describes the function of the individual bit values in the Data register, one of the two registers accessed through the serial port. The assignments are summarized in the Bit Assignments table. D0 - Register Select Indicates which register should receive the data. For the Data register, this is set to 0. D1 through D6 - Bridge 1 Linear DAC These six bits set the desired current level for Bridge 1. Setting all six bits 10 Synchronous Rectification When a PWM off-cycle is triggered, load current recirculates according to the decay mode selected by the control logic. The synchronous rectification feature turns on the appropriate MOSFETs during the current decay and effectively shorts out the body diodes with the low RDS(ON) of the MOSFET. This lowers power dissipation significantly and eliminates the need for additional Schottky diodes. Synchronous rectification can be set to one of three distinct modes by programming the Synchronous Rectification bits in the Control register (Word1, Bits D14 through D15) using the serial port. The modes are: * Active This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. * Passive This mode allows reversal of current, but will turn of the synchronous rectifier circuit if the load current inversion ramps up to the current limit, ITripDAC. * Disabled During this mode, MOSFET switching does not occur during load recirculation. Usually, this setting would only be used with 4 additional external clamp diodes per bridge. Shutdown Operation In the event of an overtemperature fault, or an undervoltage fault on VREG, the gate drive outputs are disabled until the fault condition is removed. At power-up, and in the event of low voltage at VDD, the under voltage lockout (UVLO) circuit disables the gate drive outputs until the voltage at VDD reaches the minimum level. Once VDD is above the minimum level, the data in the serial port is reset to all 0s, ensuring a safe power-up condition. Serial Interface The A3985 is controlled by a 3-wire serial port using data, clock and strobe inputs on the SDI, SCK and STR pins respectively. An additional serial data output on SDO can Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver to 0 disables Bridge 1, with all drivers off (see Internal PWM Current Control, in the Functional Description section). D7 - Bridge 1 Phase Controls the direction of output current for Bridge (load) 1. D7 0 1 S1A L H S1B H L Control Register (Word 1) Bit Assignments This section describes the function of the individual bit values in the Control register, one of the two registers accessed through the serial port. The assignments are summarized in the Bit Assignments table. Note that the Control register can only be updated when the WC pin is logic low. D0 - Register Select Indicates which register should receive the data. For the Control register, this is set to 1. D1 and D2 - Blank Time These two bits set the value of the scaling factor, / fMCK, used for determining tBLANK for the current-sense comparator. The factor for tDEAD also is set, because tDEAD = tBLANK / 2 . D2 0 0 1 1 D1 0 1 0 1 tBLANK 4 / fMCK 6 / fMCK 8 / fMCK 12 / fMCK tDEAD (tBLANK/ 2) 2 / fMCK 3 / fMCK 4 / fMCK 6 / fMCK D8 - Bridge 1 Mode Determines whether slow decay is forced or mixed decay, according to Word 1 Bits D3 to D11, is allowed. D8 0 1 Mode Mixed-decay Slow-decay D9 - D14 Bridge 2 Linear DAC These six bits set the desired current level for Bridge 2. Setting all six bits to 0 disables Bridge 2, with all drivers off (see Internal PWM Current Control, in the Functional Description section). D15 - Bridge 2 Phase Controls the direction of output current for Bridge (load) 2. D15 0 1 S2A L H S2B H L D16 - Bridge 2 Mode Determines whether slow decay is forced or mixed decay, according to Word 1 Bits D3 to D11, is allowed. D16 0 1 Mode Mixed-decay Slow-decay D3 through D7 - Fixed Off Time These five bits set the fixed off-time for the internal PWM control circuitry. Fixed off-time is defined by: tOFF = [(1 + n) x (8 / fMCK)] - 1 / fMCK , where n = 0 to 31. For example, with a master clock frequency of 4 MHz, the fast-decay time would be adjustable within the range 1.75 to 63.75 s, in increments of 2 s. D8 through D11 - Fast Decay Time These four bits set the fast decay portion of fixed off-time for the internal PWM control circuitry. The fast-decay portion is defined by: tFD = [(1 + n) x 8 / fMCK)] - 1 / fMCK , where n = 0 to 15. For example, with a master clock frequency of 4 MHz, the fast decay time would be adjustable within the range 1.75 to 32.75 s, in increments of 2 s. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com D17 and D18 - Gm Range Select These bits determine the range scaling factor, Gm , used in PWM current control, according to the following formula: ITripDAC = VDAC / (Gm x RSENSEx) D18 0 0 1 1 D17 0 1 0 1 Gm 8 12 16 20 11 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver Note that, for tFD > tOFF , the device effectively operates in full fast-decay mode. D12 and D13 - Master Clock Control An internal oscillator can be used for the timing functions, and if more precise control is required, an external clock can be input to the OSC terminal (for configuration information, refer to the Functional Description section). To accommodate a wider range of external system clocks, an internal divider is provided to generate the desired master clock frequency, fMCK , according to the following table: D13 0 0 1 1 D12 0 1 0 1 Master Clock Source and fMCK Internal oscillator* External clock rate External clock rate / 2 External clock rate / 4 D14 and D15 - Synchronous Rectification Two bits are used to set the mode for sunchronous rectification. The modes are described in the synchronous rectification section of the Functional Description section. D15 0 0 1 1 D14 0 1 0 1 Synchronous Rectification Mode Disabled Disabled Active Passive D16 and D17 - Reserved These bits are reserved for testing and should be programmed to 0 during normal operation. D18 - Idle Mode The device can be placed in a low power mode by writing a 0 to D18. This disables the outputs and the device draws a lower load supply current. The undervoltage monitor circuit remains active. When leaving idle mode, D18 should be set to 1 for 1 ms before attempting to enable any output driver. *4 MHz typical, configurable with external resistor, ROSC. Bit Assignments Table Data Register Word Bit Function D0 Register Select = 0 D1 Bridge 1, DAC bit 0 (LSB) D2 Bridge 1, DAC bit 1 D3 Bridge 1, DAC bit 2 D4 Bridge 1, DAC bit 3 D5 Bridge 1, DAC bit 4 D6 Bridge 1, DAC bit 5 (MSB) D7 Bridge 1, Phase D8 Bridge 1, Mode 0 D9 Bridge 2, DAC bit 0 (LSB) D10 Bridge 2, DAC bit 1 D11 Bridge 2, DAC bit 2 D12 Bridge 2, DAC bit 3 D13 Bridge 2, DAC bit 4 D14 Bridge 2, DAC bit 5 (MSB) D15 Bridge 2, Phase D16 Bridge 2, Mode D17 Range Select bit 0 D18 Range Select bit 1 Word 1 Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Control Register Function Register Select = 1 Blank-time bit 0 (LSB) Blank-time bit 1 (MSB) Off-time bit 0 (LSB) Off-time bit 1 Off-time bit 2 Off-time bit 3 Off-time bit 4 (MSB) Fast-decay time bit 0 (LSB) Fast-decay time bit 1 Fast-decay time bit 2 Fast-decay time bit 3 (MSB) Master Clock Control bit 0 (LSB) Master Clock Control bit 1 (MSB) Synchronous Rectification Control bit 0 (LSB) Synchronous Rectification Control bit 1 (MSB) Reserved Reserved Idle Mode Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 12 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver Applications Information Current Sensing To minimize inaccuracies in sensing the IPEAK current level caused by ground-trace IR drops, the sense resistor, RSENSEx, should have an independent return to the supply ground star point. For low-value sense resistors, the IR drops in the sense resistor PCB traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RENSESx due to their contact resistance. 3. The GND pin should be connected by an independent lowimpedance trace to the supply common at a single point. 4. Check the peak voltage excursion of the transients on the LSS pin with reference to the GND pin using a close grounded (tip and barrel) probe. If the voltage at LSS exceeds the specified absolute maximum add additional clamping, capacitance, or both, between the LSS pin and the AGND pin. Other layout recommendations: 1. Gate charge drive paths and gate discharge return paths may carry transient current pulses. Therefore, the traces from GHxx, GLxx, Sxx, and LSSx should be as short as possible to reduce the inductance of the circuit trace. 2. Provide an independent connection from each LSS pin to the common point of each power bridge. It is not recommended to connect LSS directly to the GND pin. The LSS connection should not be used for the SENSE connection. 3. Minimize stray inductance by using short, wide copper runs at the drain and source terminals of all power FETs. This includes motor lead connections, the input power bus, and the common source of the low-side power FETs. This will minimize voltages induced by fast switching of large load currents. 4. Consider the use of small (100nF) ceramic decoupling capacitors across the source and drain of the power FETs to limit fast transient voltage spikes caused by trace inductance. The above are only recommendations. Each application is different and may encounter different sensitivities. Each design should be tested at the maximum current, to ensure any parasitic effects are eliminated. Thermal Protection All drivers are turned off when the junction temperature reaches 165C typical. This is intended only to protect the A3985 from failures due to excessive junction temperatures. Thermal protection will not protect the A3985 from continuous short circuits. Thermal shutdown has a hysteresis of approximately 15C. Circuit Layout Since this is a switch-mode application, where rapid current changes are present, care must be taken during layout of the application PCB. The following points are provided as guidance for layout. Following all guidelines will not always be possible. However, each point should be carefully considered as part of any layout procedure. Ground Connection Layout Recommendations: 1. Decoupling capacitors for the supply pins VBB, VREG, and VDD should be connected independently, close to the GND pin, and not to any ground plane. The decoupling capacitors should also be connected as close as possible to the corresponding supply pin. 2. If used, the oscillator timing resistor ROSC should be connected to the GND pin. It should not be connected to any ground plane, supply common, or the power ground. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 13 A3985 Pin-out Diagram C2A 1 GH2A 2 S2A 3 GL2A 4 NC 5 VREG 6 VBB 7 GL1A 8 S1A 9 GH1A 10 C1A 11 C1B 12 GH1B 13 S1B 14 GL1B 15 LSS1 16 SENSE1 17 NC 18 ENABLE 19 Digitally Programmable Dual Full-Bridge MOSFET Driver 38 C2B 37 GH2B Bridge 2 Control 36 S2B 35 GL2B 34 NC 33 LSS2 32 SENSE2 31 WC 30 SDO Serial Interface 29 SDI 28 STR 27 SCK 26 NC Bridge 1 Control 25 VDD 24 NC 23 OSC 22 NC 21 REF 20 GND Terminal List Table Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name C2A GH2A S2A GL2A NC VREG VBB GL1A S1A GH1A C1A C1B GH1B S1B GL1B LSS1 SENSE1 NC ENABLE GND REF NC OSC NC VDD NC SCK STR SDI SDO WC SENSE2 LSS2 NC GL2B S2B GH2B C2B Description Phase 2 bootstrap capacitor drive A connection Phase 2 high-side gate drive A Phase 2 motor connection A Phase 2 low-side gate drive A No internal connection Regulator decoupling capacitor connection Motor supply voltage Phase 1 low-side gate drive A Phase 1 motor connection A Phase 1 high-side gate drive A Phase 1 bootstrap capacitor drive A connection Phase 1 bootstrap capacitor drive B connection Phase 1 high-side gate drive B Phase 1 motor connection B Phase 1 low-side gate drive B Phase 1 low-side source connection Phase 1 bridge current sense input No internal connection Output enable Ground Reference voltage No internal connection External clock input, ROSC resistor connection No internal connection Logic supply voltage No internal connection Serial Data Clock Serial Data Strobe Serial Data Input Serial Data Output Write Configuration Enable Phase 2 bridge current sense input Phase 2 low-side source connection No internal connection Phase 2 low-side gate drive B Phase 2 motor connection B Phase 2 high-side gate drive B Phase 2 bootstrap capacitor drive B connection Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 14 A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver LD Package, 38-Pin TSSOP 9.8 9.6 .386 .378 A B 8 0 0.20 .008 0.09 .004 4.5 4.3 .177 .169 6.6 6.2 .260 .244 38 0.75 .030 0.45 .018 1 .039 REF A 12 0.25 .010 38X 0.10 [.004] C 38X 0.27 .011 0.17 .007 0.08 [.003] M C A B 0.50 .020 SEATING PLANE 1.20 .047 MAX 0.15 .006 0.00 .000 0.30 .012 NOM 36X 0.20 .008 MIN C SEATING PLANE GAUGE PLANE 1.85 .073 NOM 38 0.50 .020 NOM Preliminary dimensions, for reference only (reference JEDEC MO-153 BD-1) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 TSSOP50P640X120-38M); adjust as necessary to meet application process requirements and PCB layout tolerances B 5.9 .232 NOM 12 The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c)2005, 2006 AllegroMicrosystems, Inc. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 15 |
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